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ltc4274a/ltc4274c 1 4274acfc n ltpoe ++ pse switches/routers n ltpoe ++ pse midspans n ieee 802.3at type 1 pse switches/routers n ieee 802.3at type 1 pse midspans applications features description single poe/poe + /ltpoe ++ pse controller the ltc ? 4274a is a single power sourcing equipment (pse) controller capable of delivering up to 90w of ltpoe ++ power to a compatible ltpoe ++ powered device (pd). a proprietary detection/classification scheme allows mutual identification between a ltpoe ++ pse and ltpoe ++ pd while remaining compatible and interoperable with existing type 1 (13w) and type 2 (25.5w) pds. the ltc4274a feature set is a superset of the popular ltc4274. these pse controllers feature low-r on external mosfets and 0.25 sense resistors which are especially important at the ltpoe ++ current levels to maintain the lowest possible heat dissipation. the ltc4274c targets fully automatic pse systems power- ing type 1 (up to 13w) pds. advanced power management features include: a 14-bit current monitoring adc, dac-programmable current limit, and versatile quick port shutdown. pd discovery uses a proprietary dual-mode 4-point detection mechanism ensuring excellent immunity from false pd detection. the ltc4274a/ltc4274c includes an i 2 c serial interface operable up to 1mhz. the ltc4274a/ltc4274c is available in multiple power grades, allowing delivered pd power of 13w, 25.5w, 38.7w, 52.7w, 70w and 90w. these controllers are available in a 38-lead 5mm 7mm qfn package. n compliant with ieee 802.3at type 1 and 2 n low power dissipation 0.25 sense resistance per channel n very high reliability 4-point pd detection 2-point forced voltage 2-point forced current n high capacitance legacy device detection n 1mhz i 2 c compatible serial control interface n midspan backoff timer n supports 2-pair and 4-pair output power n available in multiple power grades ltc4274a-1: ltpoe ++ ? 38.7w ltc4274a-2: ltpoe ++ 52.7w ltc4274a-3: ltpoe ++ 70w ltc4274a-4: ltpoe ++ 90w ltc4274c: poe 13w n available in 38-lead 5mm 7mm qfn package typical application complete single-port ethernet high power source l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and ltpoe ++ are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 4274ac ta01 scl sdain sdaout ad0 ad1 ad2 ad3 agnd v ee sense C54v 1f 100v smaj58a gate out port 0.22f 100v s1b s1b C54v dgnd v dd int shdn auto msd reset mid 0.1f 3.3v ltc4274a/ltc4274c
ltc4274a/ltc4274c 2 4274acfc absolute maximum ratings pin configuration order information lead free finish tape and reel part marking package description max pwr temperature range ltc4274ciuhf#pbf ltc4274ciuhf#trpbf 4274c 38-lead (5mm 7mm) plastic qfn 13w C40c to 85c ltc4274aiuhf-1#pbf ltc4274aiuhf-1#trpbf 4274a1 38-lead (5mm 7mm) plastic qfn 38.7w C40c to 85c ltc4274aiuhf-2#pbf ltc4274aiuhf-2#trpbf 4274a2 38-lead (5mm 7mm) plastic qfn 52.7w C40c to 85c ltc4274aiuhf-3#pbf ltc4274aiuhf-3#trpbf 4274a3 38-lead (5mm 7mm) plastic qfn 70w C40c to 85c ltc4274aiuhf-4#pbf ltc4274aiuhf-4#trpbf 4274a4 38-lead (5mm 7mm) plastic qfn 90w C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 13 14 15 16 top view v ee 39 uhf package 38-lead (5mm = 7mm) plastic qfn exposed pad is v ee (pin 39) must be soldered to pcb t jmax = 125c, e ja = 34c/w 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1sdaout nc sdain ad3 ad2 ad1 ad0 dnc nc dgnd nc nc gate sense nc nc v ee v ee v ee nc nc v ee nc nc scl int mid reset msd auto out v dd shdn dgnd dgnd dgnd agnd v ee 23 22 21 20 9 10 11 12 supply voltages (note 1) agnd C v ee ........................................... C0.3v to 80v dgnd C v ee ........................................... C0.3v to 80v v dd C dgnd ......................................... C0.3v to 5.5v digital pins scl, sdain, sdaout, int , shdn , msd , ad, reset , auto, mid ........... dgnd C0.3v to v dd + 0.3v analog pins gate, sense, out ................ v ee C0.3v to v ee + 80v operating temperature range ................. C40c to 85c junction temperature (note 2) ............................. 125c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) ................... 300c
ltc4274a/ltc4274c 3 4274acfc electrical characteristics symbol parameter conditions min typ max units v ee main poe supply voltage agnd C v ee for ieee type 1 compliant output for ieee type 2 compliant output for ltpoe ++ compliant output l l l 45 51 54.75 57 57 57 v v v undervoltage lockout agnd C v ee l 20 25 30 v v dd v dd supply voltage v dd C dgnd l 3.0 3.3 4.3 v undervoltage lockout l 2.2 v allowable digital ground offset dgnd C v ee l 25 57 v i ee v ee supply current (agnd C v ee ) = 55v l C2.4 C5 ma i dd v dd supply current (v dd C dgnd) = 3.3v l 1.1 3 ma detection detection current C force current first point, agnd C v out = 9v second point, agnd C v out = 3.5v l l 220 140 240 160 260 180 a a detection voltage C force voltage agnd C v out , 5a i out 500a first point second point l l 7 3 8 4 9 5 v v detection current compliance agnd C v out = 0v l 0.8 0.9 ma v oc detection voltage compliance agnd C v out , open port l 10.4 12 v detection voltage slew rate agnd C v out , c port = 0.15f l 0.01 v/s minimum valid signature resistance l 15.5 17 18.5 k maximum valid signature resistance l 27.5 29.7 32 k classification v class classification voltage agnd C v out , 0ma i class 50ma l 16.0 20.5 v classification current compliance v out = agnd l 53 61 67 ma classification threshold current class 0 C 1 class 1 C 2 class 2 C 3 class 3 C 4 class 4 C overcurrent l l l l l 5.5 13.5 21.5 31.5 45.2 6.5 14.5 23 33 48 7.5 15.5 24.5 34.9 50.8 ma ma ma ma ma v mark classification mark state voltage agnd C v out , 0.1ma i class 10ma l 7.5 9 10 v mark state current compliance v out = agnd l 53 61 67 ma gate driver gate pin pull-down current port off, v gate = v ee + 5v port off, v gate = v ee + 1v l l 0.4 0.08 0.12 ma ma gate pin fast pull-down current v gate = v ee + 5v 30 ma gate pin on voltage v gate C v ee , i gate = 1a l 81214 v output voltage sense v pg power good threshold voltage v out C v ee l 2 2.4 2.8 v out pin pull-up resistance to agnd 0v (agnd C v out ) 5v l 300 500 700 k the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. agnd C v ee = 54v, agnd = dgnd, and v dd C dgnd = 3.3v unless otherwise noted. (notes 3, 4)
ltc4274a/ltc4274c 4 4274acfc symbol parameter conditions min typ max units current sense v cut overcurrent sense voltage v sense C v ee , hpen = 01h, cut[5:0] 4 (note 12) cutrng = 0 cutrng = 1 l l 9 4.5 9.38 4.69 9.75 4.88 mv/lsb mv/lsb overcurrent sense in auto pin mode class 0, class 3 class 1 class 2 class 4 l l l l 90 26 49 152 94 28 52 159 98 30 55 166 mv mv mv mv v lim active current limit in 802.3af compliant mode v sense C v ee , hpen = 01h, lim = 80h, v ee = 55v (note 12) v ee < v out < agnd C 29v agnd C v out = 0v l l 102 20 106 110 50 mv mv v lim active current limit in high power mode hpen = 01h, lim = c0h, v ee = 55v v out C v ee = 0v to 10v v ee + 23v < v out < agnd C 29v agnd C v out = 0v l l l 204 100 20 212 106 221 113 50 mv mv mv v lim active current limit in auto pin mode v out C v ee = 0v to 10v, v ee = 55v class 0 to class 3 class 4 l l 102 204 106 212 110 221 mv mv v min dc disconnect sense voltage v sense C v ee , rdis = 0 v sense C v ee , rdis = 1 l l 2.6 1.3 3.8 1.9 4.8 2.41 mv mv v sc short-circuit sense v sense C v ee C v lim , rdis = 0 v sense C v ee C v lim , rdis = 1 l l 160 75 200 100 255 135 mv mv port current readback resolution no missing codes, fast_iv = 0 14 bits lsb weight v sense C v ee 30.5 v/lsb 50hz to 60hz noise rejection (note 7) 30 db port voltage readback resolution no missing codes, fast_iv = 0 14 bits lsb weight agnd C v out 5.835 mv/lsb 50hz to 60hz noise rejection (note 7) 30 db digital interface v ild digital input low voltage adn, shdn, reset, msd, auto, mid (note 6) l 0.8 v i 2 c input low voltage scl, sdain (note 6) l 0.8 v v ihd digital input high voltage (note 6) l 2.2 v digital output low voltage i sdaout = 3ma, i int = 3ma i sdaout = 5ma, i int = 5ma l l 0.4 0.7 v v internal pull-up to v dd adn, shdn, reset, msd 50 k internal pull-down to dgnd auto, mid 50 k electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. agnd C v ee = 54v, agnd = dgnd, and v dd C dgnd = 3.3v unless otherwise noted. (notes 3, 4)
ltc4274a/ltc4274c 5 4274acfc symbol parameter conditions min typ max units timing characteristics t det detection time beginning to end of detection (note 7) l 270 290 310 ms t detdly detection delay from pd connected to port to detection complete (note 7) l 300 470 ms t cle class event duration (note 7) l 12 ms t cleon class event turn-on duration c port = 0.6f (note 7) l 0.1 ms t me mark event duration (notes 7, 11) l 8.6 ms t mel last mark event duration (notes 7, 11) l 16 22 ms t pon power on delay in auto pin mode from end of valid detect to application of power to port (note 7) l 60 ms turn on rise time (agnd C v out ): 10% to 90% of (agnd C v ee ), c port = 0.15f (note 7) l 15 24 s turn on ramp rate c port = 0.15f (note 7) l 10 v/s fault delay from i cut fault to next detect l 1.0 1.1 s midspan mode detection backoff rport = 15.5k (note 7) l 2.3 2.5 2.7 s power removal detection delay from power removal after t dis to next detect (note 7) l 1.0 1.3 2.5 s t start maximum current limit duration during port start-up (note 7) l 52 62.5 66 ms t lim maximum current limit duration after port start-up t lim enable = 1 (notes 7, 12) l 11.9 ms t cut maximum overcurrent duration after port start-up (note 7) l 52 62.5 66 ms maximum overcurrent duty cycle (note 7) l 5.8 6.3 6.7 % t mps maintain power signature (mps) pulse width sensitivity current pulse width to reset disconnect timer (notes 7, 8) l 1.6 3.6 ms t dis maintain power signature (mps) dropout time (notes 5, 7) l 320 350 380 ms t msd masked shut down delay (note 7) l 6.5 s t shdn port shut down delay (note 7) l 6.5 s i 2 c watchdog timer duration l 1.5 2 3 s minimum pulse width for masked shut down (note 7) l 3 s minimum pulse width for shdn (note 7) l 3 s minimum pulse width for reset (note 7) l 4.5 s electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. agnd C v ee = 54v, agnd = dgnd, and v dd C dgnd = 3.3v unless otherwise noted. (notes 3, 4)
ltc4274a/ltc4274c 6 4274acfc symbol parameter conditions min typ max units i 2 c timing clock frequency (note 7) l 1 mhz t 1 bus free time figure 5 (notes 7, 9) l 480 ns t 2 start hold time figure 5 (notes 7, 9) l 240 ns t 3 scl low time figure 5 (notes 7, 9) l 480 ns t 4 scl high time figure 5 (notes 7, 9) l 240 ns t 5 data hold time figure 5 (notes 7, 9) data into chip data out of chip l l 60 120 ns ns t 6 data set-up time figure 5 (notes 7, 9) l 80 ns t 7 start set-up time figure 5 (notes 7, 9) l 240 ns t 8 stop set-up time figure 5 (notes 7, 9) l 240 ns t r scl, sdain rise time figure 5 (notes 7, 9) l 120 ns t f scl, sdain fall time figure 5 (notes 7, 9) l 60 ns fault present to int pin low (notes 7, 9, 10) l 150 ns stop condition to int pin low (notes 7, 9, 10) l 1.5 s ara to int pin high time (notes 7, 9) l 1.5 s scl fall to ack low (notes 7, 9) l 120 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 140c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 3: all currents into device pins are positive; all currents out of device pins are negative. note 4: the ltc4274a/ltc4274c operates with a negative supply voltage (with respect to ground). to avoid confusion, voltages in this data sheet are referred to in terms of absolute magnitude. note 5: t dis is the same as t mpdo defined by ieee 802.3at. note 6: the ltc4274a/ltc4274c digital interface operates with respect to dgnd. all logic levels are measured with respect to dgnd. note 7: guaranteed by design, not subject to test. note 8: the ieee 802.3af specification allows a pd to present its maintain power signature (mps) on an intermittent basis without being disconnected. in order to stay powered, the pd must present the mps for t mps within any t mpdo time window. note 9: values measured at v ild(max) and v ihd(min) . note 10: if fault condition occurs during an i 2 c transaction, the int pin will not be pulled down until a stop condition is present on the i 2 c bus. note 11: load characteristic of the ltc4274a/ltc4274c during mark: 7v < (agnd C v out ) < 10v or i out < 50a note 12: see the ltc4274a/ltc4274c software programming documentation for information on serial bus usage and device configuration and status registers. electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. agnd C v ee = 54v, agnd = dgnd, and v dd C dgnd = 3.3v unless otherwise noted. (notes 3, 4)
ltc4274a/ltc4274c 7 4274acfc typical performance characteristics power-on sequence in auto pin mode powering up into a 180f load 802.3af classification in auto pin mode 2-event classification in auto pin mode classification transient response to 40ma load step classification current compliance v dd supply current vs voltage v ee supply current vs voltage 802.3at i lim threshold vs temperature 100ms/div C70 C60 port voltage (v) 10 0 C10 C20 C30 C40 C50 4274ac g01 v dd = 3.3v v ee = C54v forced current detection forced voltage detection 802.3af classification power on gnd v ee 5ms/div gnd 0ma 4274ac g02 v ee v ee gate voltage 10v/div port current 200 ma/div port voltage 20v/div foldback fet on 425ma current limit load fully charged v dd = 3.3v v ee = C54v 5ms/div v ee C18.4 port voltage 10v/div gnd 4274ac g03 v dd = 3.3v v ee = C55v pd is class 1 10ms/div v ee C17.6 port voltage 10v/div gnd 4274ac g04 v dd = 3.3v v ee = C55v pd is class 4 1st class event 2nd class event 50s/div 40ma 0ma 4274ac g05 C20v port voltage 1v/div port current 20ma/div v dd = 3.3v v ee = C54v classification current (ma) C20 classification voltage (v) C18 C16 C14 C12 C10 C8 C6 C4 C2 0 0102030 4274ac g06 40 50 60 70 v dd = 3.3v v ee = C54v t a = 25c v dd supply voltage (v) 2.7 0.8 i dd supply current (ma) 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 2.9 3.1 3.3 3.5 4274ac g07 3.7 3.9 4.1 4.3 85c 25c C40c v ee supply voltage (v) C60 2.0 i ee supply current (ma) 2.1 2.2 2.3 2.4 C55 C50 C45 C40 4274ac g08 C35 C30 C25 C20 85c 25c C40c temperature (c) C40 210 v lim (mv) i lim (ma) 211 213 212 214 215 840 844 852 848 856 860 040 4274ac g09 C80 120 v dd = 3.3v v ee = C54v r sense = 0.25 reg 48h = c0h
ltc4274a/ltc4274c 8 4274acfc typical performance characteristics 802.3af i lim threshold vs temperature dc disconnect threshold vs temperature current limit foldback adc noise histogram current readback in fast mode adc integral nonlinearity current readback in fast mode 802.3at i cut threshold vs temperature 802.3af i cut threshold vs temperature temperature (c) C40 105.00 v lim (mv) i lim (ma) 106.50 105.75 107.25 108.00 420 423 426 429 432 040 4274ac g10 80 120 v dd = 3.3v v ee = C54v r sense = 0.25 reg 48h = 80h temperature (c) C40 158 v cut (mv) i cut (ma) 161 160 159 162 163 630 636 640 648 644 652 040 4274ac g11 80 120 v dd = 3.3v v ee = C54v r sense = 0.25 reg 47h = e2h temperature (c) C40 93.00 v cut (mv) i cut (ma) 94.50 93.75 95.25 96.00 372 375 378 381 384 040 4274ac g12 80 120 v dd = 3.3v v ee = C54v r sense = 0.25 reg 47h = d4h temperature (c) C40 v min (mv) i min (mv) 7.00 7.50 7.25 7.75 8.00 1.7500 1.8125 1.8750 1.9375 2.0000 040 4274ac g13 80 120 v dd = 3.3v v ee = C54v r sense = 0.25 reg 47h = e2h v outn (v) C54 0 i lim (ma) v lim (mv) 900 800 700 600 500 400 300 200 100 0 225 200 175 150 125 100 75 50 25 C36C45 C27 4274ac g14 C18 C9 0 v dd = 3.3v v ee = C54v r sense = 0.25 reg 48h = c0h adc output 191 0 b in count 400 350 300 250 200 150 100 50 193192 194 4274ac g15 195 196 v sense C v ee = 110.4mv current sense resistor input voltage (mv) 0 adc integral nonlinearity (lsbs) 0 0.5 400 4274ac g16 C0.5 C1.0 100 200 250 500 1.0 300 50 150 450 350
ltc4274a/ltc4274c 9 4274acfc typical performance characteristics adc noise histogram current readback in slow mode adc integral nonlinearity current readback in slow mode adc noise histogram port voltage readback in fast mode adc integral nonlinearity voltage readback in fast mode adc noise histogram port voltage readback in slow mode adc integral nonlinearity voltage readback in slow mode int and sdaout pull-down voltage vs load current mosfet gate drive with fast pull-down adc output 0 b in count 300 250 200 150 100 50 6139 6141 4274ac g17 6143 6145 6147 v sense C v ee = 110.4mv current sense resistor input voltage (mv) 0 adc integral nonlinearity (lsbs) 0 0.5 400 4274ac g18 C0.5 C1.0 100 200 250 500 1.0 300 50 150 450 350 adc output 260 0 b in count 600 500 400 300 200 100 262261 263 4274ac g19 264 265 agnd C v out = 48.3v port voltage (v) 0 adc integral nonlinearity (lsbs) 0 0.5 50 4274ac g20 C0.5 C1.0 20 30 60 1.0 40 10 adc output 8532 0 b in count 600 500 400 300 200 100 8534 8533 8535 4274ac g21 8536 agnd C v out = 48.3v port voltage (v) 0 adc integral nonlinearity (lsbs) 0 0.5 50 4274ac g22 C0.5 C1.0 20 30 60 1.0 40 10 load current (ma) 0 0 pull-down voltage (v) 3 2.5 2 1.5 1 0.5 10 5 15 4274ac g23 20 25 30 35 40 100s/div gnd 0ma 4274ac g24 v ee v ee port current 500ma/div gate voltage 10v/div port voltage 20v/div current limit 50 fault removed 50 fault applied v dd = 3.3v v ee = C54v fast pull-down
ltc4274a/ltc4274c 10 4274acfc test timing diagrams figure 1. detect, class and turn-on timing in auto pin or semi-auto modes figure 2. current limit timing figure 3. dc disconnect timing v port int v oc v ee t det t me t mel v mark v class 15.5v 20.5v t cle t cle t cleon pd connected 0v 4274ac f01 forced-current classification t pon forced- voltage v lim v cut 0v v sense to v ee int 4274ac f02 t start , t icut v min v sense to v ee int t dis t mps 4274ac f03
ltc4274a/ltc4274c 11 4274acfc test timing diagrams figure 4. shut down delay timing figure 5. i 2 c interface timing v gate v ee msd or shdn t shdn t msd 4274ac f04 scl sda t 1 t 2 t 3 t r t f t 5 t 6 t 7 t 8 t 4 4274ac f05
ltc4274a/ltc4274c 12 4274acfc i 2 c timing diagrams figure 6. writing to a register figure 7. reading from a register scl sda 4274ac f06 00 1 ad3 ad2 ad1 ad0 a7 a6 a5 a4 a3 a2 a1 a0 r/w ack d7 d6 d5 d4 d3 d2 d1 d0 ack ack start by master ack by slave ack by slave ack by slave frame 1 serial bus address byte frame 2 register address byte frame 3 data byte stop by master scl sda 00 1 ad3 ad2 ad1 ad0 a7 a6 a5 a4 a3 a2 a1 a0 r/w ack ack 00 1 ad3 ad2 ad1 ad0 d7 d6 d5 d4 d3 d2 d1 d0 r/w ack ack start by master ack by slave ack by slave 4274ac f07 stop by master repeated start by master ack by slave no ack by master frame 1 serial bus address byte frame 2 register address byte frame 1 serial bus address byte frame 2 data byte
ltc4274a/ltc4274c 13 4274acfc figure 8. reading the interrupt register (short form) figure 9. reading from alert response address i 2 c timing diagrams scl sda 4274ac f08 01 0 ad3 ad2 ad1 ad0 d7 d6 d5 d4 d3 d2 d1 d0 r/w ack ack start by master ack by slave no ack by master frame 1 serial bus address byte frame 2 data byte stop by master scl sda 4274ac f09 00 1 1 0 ad30 0 00 1 ad2 ad1 ad0 r/w ack ack1 start by master ack by slave no ack by master frame 1 alert response address byte frame 2 serial bus address byte stop by master
ltc4274a/ltc4274c 14 4274acfc pin functions reset: chip reset, active low. when the reset pin is low, the ltc4274a/ltc4274c is held inactive with the port off and all internal registers reset to their power-up states. when reset is pulled high, the ltc4274a/ltc4274c begins normal operation. reset can be connected to an external capacitor or rc network to provide a power turn-on delay. internal filtering of the reset pin prevents glitches less than 1s wide from resetting the ltc4274a/ ltc4274c. internally pulled up to v dd . mid: midspan mode input. when high, the ltc4274a/ ltc4274c acts as a midspan device. internally pulled down to dgnd. int: interrupt output, open drain. int will pull low when any one of several events occur in the ltc4274a/ltc4274c. it will return to a high impedance state when bits 6 or 7 are set in the reset pb register (1ah). the int signal can be used to generate an interrupt to the host processor, eliminating the need for continuous software polling. individual int events can be disabled using the int mask register (01h). see the ltc4274a/ltc4274c software programming documentation for more information. the int pin is only updated between i 2 c transactions. scl: serial clock input. high impedance clock input for the i 2 c serial interface bus. scl must be tied high if not used. sdaout: serial data output, open drain data output for the i 2 c serial interface bus. the ltc4274a/ltc4274c uses two pins to implement the bidirectional sda function to simplify optoisolation of the i 2 c bus. to implement a standard bidirectional sda pin, tie sdaout and sdain together. sdaout should be grounded or left floating if not used. see the applications information section for more information. sdain: serial data input. high impedance data input for the i 2 c serial interface bus. the ltc4274a/ltc4274c uses two pins to implement the bidirectional sda function to simplify optoisolation of the i 2 c bus. to implement a standard bidirectional sda pin, tie sdaout and sdain together. sdain must be tied high if not used. see the applications information section for more information. ad3: address bit 3. tie the address pins high or low to set the i 2 c serial address to which the ltc4274a/ltc4274c responds. this address will be 010a 3 a 2 a 1 a 0 b. internally pulled up to v dd . ad2: address bit 2. see ad3. ad1: address bit 1. see ad3. ad0: address bit 0. see ad3. nc, dnc: all pins identified with nc or dnc must be left unconnected. dgnd: digital ground. dgnd is the return for the v dd supply. v dd : logic power supply. connect to a 3.3v power supply relative to dgnd. v dd must be bypassed to dgnd near the ltc4274a/ltc4274c with at least a 0.1f capacitor. shdn: shutdown, active low. when pulled low, shdn shuts down the port, regardless of the state of the internal registers. pulling shdn low is equivalent to setting the reset port bit in the reset pushbutton register (1ah). internal filtering of the shdn pin prevents glitches less than 1s wide from resetting the port. internally pulled up to v dd . agnd: analog ground. agnd is the return for the v ee supply. sense: current sense input. sense monitors the exter- nal mosfet current via a 0.5 or 0.25 sense resistor between sense and v ee . whenever the voltage across the sense resistor exceeds the overcurrent detection threshold v cut , the current limit fault timer counts up. if the voltage across the sense resistor reaches the current limit threshold v lim , the gate pin voltage is lowered to maintain constant current in the external mosfet. see the applications information section for further details.
ltc4274a/ltc4274c 15 4274acfc overview power over ethernet, or poe, is a standard protocol for sending dc power over copper ethernet data wiring. the ieee group that administers the 802.3 ethernet data standards added poe powering capability in 2003. this original poe spec, known as 802.3af, allowed for 48v dc power at up to 13w. this initial spec was widely popular, but 13w was not adequate for some requirements. in 2009, the ieee released a new standard, known as 802.3at or poe + , increasing the voltage and current requirements to provide 25w of power. the ieee standard also defines poe terminology. a device that provides power to the network is known as a pse, or power sourcing equipment, while a device that draws power from the network is known as a pd, or powered device. pses come in two types: endpoints (typically network switches or routers), which provide data and power; and midspans, which provide power but pass through data. midspans are typically used to add poe capability to existing non-poe networks. pds are typically ip phones, wireless access points, security cameras, and similar devices. poe ++ evolution even during the process of creating the ieee poe + 25.5w specification, it became clear that there was a significant and increasing need for more than 25.5w of delivered power. the ltc4274a family responds to this market by allowing a reliable means of providing up to 90w of deliv- ered power to a ltpoe ++ pd. the ltpoe ++ specification provides reliable detection and classification extensions to the existing ieee poe technique that are backward com- patible and interoperable with existing type 1 and type 2 pds. unlike other proprietary poe ++ solutions, linears ltpoe ++ solution provides mutual identification between the pse and pd. this ensures that the ltpoe ++ pd knows it may use the requested power at start-up because it has detected a ltpoe ++ pse. ltpoe ++ pses can differentiate between a ltpoe ++ pd and all other types of ieee compli- ant pds allowing ltpoe ++ pses to remain compliant and interoperable with existing equipment. pin functions gate: gate drive. gate should be connected to the gate of the external mosfet for the port. when the mosfet is turned on, the gate voltage is driven to 12v (typ) above v ee . during a current limit condition, the voltage at gate will be reduced to maintain constant current through the external mosfet. if the fault timer expires, gate is pulled down, turning the mosfet off and recording a t cut or t start event. out: output voltage monitor. out should be connected to the output port. a current limit foldback circuit limits the power dissipation in the external mosfet by reduc- ing the current limit threshold when the drain-to-source voltage exceeds 10v. the power good bit is set when the voltage from out to v ee drops below 2.4v (typ). a 500k resistor is connected internally from out to agnd when the port is idle. v ee : main supply input. connect to a C45v to C57v supply, relative to agnd. auto: auto pin mode input. auto pin mode allows the ltc4274a/ltc4274c to detect and power up a pd even if there is no host controller present on the i 2 c bus. the voltage of the auto pin determines the state of the internal registers when the ltc4274a/ltc4274c is reset or comes out of v dd uvlo (see the ltc4274a/ltc4274c software programming documentation). the states of these register bits can subsequently be changed via the i 2 c interface. the real-time state of the auto pin is read at bit 0 in the pin status register (11h). internally pulled down to dgnd. must be tied locally to either v dd or dgnd. msd: maskable shutdown input. active low. when pulled low, all ports that have their corresponding mask bit set in the misc config register (17h) will be reset, equivalent to pulling the shdn pin low. internal filtering of the msd pin prevents glitches less than 1s wide from resetting ports. internally pulled up to v dd . operation
ltc4274a/ltc4274c 16 4274acfc operation figure 10. power over ethernet system diagram ltc4274 product family the ltc4274 is a third-generation single pse controller that implements four pse ports in either an end-point or midspan design. virtually all necessary circuitry is included to implement an ieee 802.3at compliant pse design, requiring only an external power mosfet and sense resistor; these minimize power loss compared to alternative designs with an on-board mosfet. the ltc4274 comes in three grades which support dif- ferent pd power levels. the a-grade ltc4274 extends poe power delivery capabili- ties to ltpoe ++ levels. ltpoe ++ is a linear technology proprietary specification allowing for the delivery of up to 90w to ltpoe ++ compliant pds. the ltpoe ++ architecture extends the ieee physical power negotiation to include 38.7w, 52.7w, 70w and 90w power levels. the a-grade ltc4274 also incorporates all b- and c-grade features. the b-grade ltc4274 is a fully ieee-compliant type 2 pse supporting autonomous detection, classification and powering of type 1 and type 2 pds. the b-grade ltc4274 also incorporates all c-grade features. the b-grade ltc4274 is marketed and numbered without the b suffix for legacy reasons; the absence of power grade suffix infers a b-grade part. the c-grade ltc4274 is a fully autonomous 802.3at type 1 pse solution. intended for use only in auto pin mode, the c-grade chipset autonomously supports detection, classification and powering of type 1 pds. as a type 1 pse, 2-event classification is prohibited and class 4 pds are automatically treated as class 0 pds. poe basics common ethernet data connections consist of two or four twisted pairs of copper wire (commonly known as cat-5 cable), transformer-coupled at each end to avoid ground loops. poe systems take advantage of this coupling ar- rangement by applying voltage between the center-taps of the data transformers to transmit power from the pse to the pd without affecting data transmission. figure 10 shows a high-level poe system schematic. to avoid damaging legacy data equipment that does not expect to see dc voltage, the poe spec defines a protocol that determines when the pse may apply and remove power. valid pds are required to have a specific 25k common-mode resistance at their input. when such a pd is connected to the cable, the pse detects this signature resistance and turns on the power. when the pd is later disconnected, the pse senses the open circuit and turns power off. the pse also turns off power in the event of a current fault or short-circuit. 4274ac f10 s1b s1b smaj58a 58v 0.22f 100v x7r 1 f 100v x7r tx rx rx tx smaj58a 58v data pair data pair v ee sense gate out v dd int scl sdain sdaout 0.25 spare pair spare pair ltc4274a/ ltc4274c dgnd agnd i 2 c 3.3v interrupt C54v ca t 5 rj45 4 5 4 5 1 2 1 2 3 6 3 6 7 8 7 8 rj45 1n4002 =4 1n4002 =4 pse pd r class v in pwrgd v out ltc4265 gnd dc/dc converter 5f c in 300f + C v out gnd 0.1 f 100v
ltc4274a/ltc4274c 17 4274acfc operation when a pd is detected, the pse optionally looks for a classification signature that tells the pse the maximum power the pd will draw. the pse can use this information to allocate power among several ports, police the current consumption of the pd, or to reject a pd that will draw more power that the pse has available. for a 802.3af pse, the classification step is optional; if a pse chooses not to classify a pd, it must assume that the pd is a 13w (full 802.3af power) device. new in 802.3at the newer 802.3at standard supersedes 802.3af and brings several new features: ? a pd may draw as much as 25.5w. such pds (and the pses that support them) are known as type 2. older 13w 802.3af equipment is classified as type 1. type 1 pds will work with all pses; type 2 pds may require type 2 pses to work properly. the ltc4274a/ltc4274c is designed to work in both type 1 and type 2 pse de- signs, and also supports non-standard configurations at higher power levels. ? the classification protocol is expanded to allow type 2 pses to detect type 2 pds, and to allow type 2 pds to determine if they are connected to a type 2 pse. two versions of the new classification protocol are avail- able: an expanded version of the 802.3af class pulse protocol, and an alternate method integrated with the existing lldp protocol (using the ethernet data path). the ltc4274a/ltc4274c fully supports the new class pulse protocol and is also compatible with the lldp protocol (which is implemented in the data communica- tions layer, not in the poe circuitry). ? fault protection current levels and timing are adjusted to reduce peak power in the mosfet during a fault; this allows the new 25.5w power levels to be reached using the same mosfets as older 13w designs. extended power ltpoe ++ the ltc4274a adds the capability to autonomously deliver up to 90w of power to the pd. ltpoe ++ pds may forego 802.3 lldp support and rely solely on the ltpoe ++ physi- cal classification to negotiate power with ltpoe ++ pses; this greatly simplifies high-power pd implementations. ltpoe ++ classification may be optionally enabled for the ltc4274a by setting both the high power enable and ltpoe ++ enable bits. the higher levels of ltpoe ++ delivery impose additional layout and component selection constraints. the ltc4274a is offered in four power levels (-1, -2, -3, and -4) which allows the auto pin mode ltc4274a to autonomously power up to supported power levels. if the auto pin is high, internal circuitry determines the maximum deliver- able power. pds requesting more than the available power limits are not powered. table 1. ltpoe ++ auto pin mode maximum delivered power capabilities part pairs pd power ltc4274a-1 4 38.7w ltc4274a-2 4 52.7w ltc4274a-3 4 70w ltc4274a-4 4 90w
ltc4274a/ltc4274c 18 4274acfc applications information operating modes the ltc4274a/ltc4274c can operate in one of four modes: manual, semi-auto, auto pin, or shutdown. table 2. operating modes mode auto pin opmd detect/ class power-up automatic i cut /i lim assignment auto pin 1 11b enabled at reset automatically yes reserved 0 11b n/a n/a n/a semi-auto 0 10b host enabled upon request no manual 0 01b once upon request upon request no shutdown 0 00b disabled disabled no ? in manual mode, the port waits for instructions from the host system before taking any action. it runs a single detection or classification cycle when commanded to by the host, and reports the result in its port status register. the host system can command the port to turn on or off the power at any time. this mode should only be used for diagnostic and test purposes. ? in semi-auto mode, the port repeatedly attempts to detect and classify any pd attached to it. it reports the status of these attempts back to the host, and waits for a command from the host before turning on power to the port. the host must enable detection (and optionally classification) for the port before detection will start. ? auto pin mode operates the same as semi-auto mode except that it will automatically turn on the power to the port if detection is successful. in auto pin mode, i cut and i lim values are set automatically by the ltc4274a/ ltc4274c. this operational mode is only valid if the auto pin is high at reset or power-up and remains high during operation. ? in shutdown mode, the port is disabled and will not detect or power a pd. regardless of which mode it is in, the ltc4274a/ltc4274c will remove power automatically from a port which gener- ates a current limit fault. it will also automatically remove power from any port that generates a disconnect event if disconnect detection is enabled. the host controller may also command the port to remove power at any time. reset and the auto/mid pins the initial ltc4274a/ltc4274c configuration depends on the state of the auto and mid pins during reset. reset occurs at power-up, or whenever the reset pin is pulled low or the global reset all bit is set. changing the state of auto or mid after power-up will not properly change the port behavior of the ltc4274a/ltc4274c until a reset occurs. although typically used with a host controller, the ltc4274a/ltc4274c can also be used in a standalone mode with no connection to the serial interface. if there is no host present, the auto pin must be tied high so that, at reset, the port will be configured to operate automatically. the port will detect and classify repeatedly until a pd is discovered, set i cut and i lim according to the classifica- tion results, apply power after successful detection, and remove power when a pd is disconnected. table 3 shows the i cut and i lim values that will be auto- matically set in standalone (auto pin) mode, based on the discovered class. table 3. i cut and i lim values in auto pin mode class i cut i lim class 1 112ma 425ma class 2 206ma 425ma class 3 or class 0 375ma 425ma class 4 638ma 850ma the automatic setting of the i cut and i lim values only occurs if the ltc4274a/ltc4274c is reset with the auto pin high. if the standalone application is a midspan, the mid pin must be tied high to enable correct midspan detection timing. detection detection overview to avoid damaging network devices that were not designed to tolerate dc voltage, a pse must determine whether the connected device is a real pd before applying power. the ieee specification requires that a valid pd have a common-mode resistance of 25k 5% at any port volt- age below 10v. the pse must accept resistances that fall
ltc4274a/ltc4274c 19 4274acfc applications information between 19k and 26.5k, and it must reject resistances above 33k or below 15k (shaded regions in figure 11). the pse may choose to accept or reject resistances in the undefined areas between the must-accept and must-reject ranges. in particular, the pse must reject standard computer network ports, many of which have 150 common-mode termination resistors that will be damaged if power is ap- plied to them (the black region at the left of figure 11). corresponding port status register. values outside this range, including open and short-circuits, are also reported. if the port measures less than 1v at the first forced-current test, the detection cycle will abort and short circuit will be reported. table 4 shows the possible detection results. table 4. detection status measured pd signature detection result incomplete or not yet tested detect status unknown <2.4k short circuit capacitance > 2.7f c pd too high 2.4k < r pd < 17k r sig too low 17k < r pd < 29k detect good >29k r sig too high >50k open circuit voltage > 10v port voltage outside detect range more on operating modes the ports operating mode determines when the ltc4274a/ ltc4274c runs a detection cycle. in manual mode, the port will idle until the host orders a detect cycle. it will then run detection, report the results, and return to idle to wait for another command. in semi-auto mode, the ltc4274a/ltc4274c autono- mously polls a port for pds, but it will not apply power until commanded to do so by the host. the port status register is updated at the end of each detection cycle. if a valid signature resistance is detected and classification is enabled, the port will classify the pd and report that result as well. the port will then wait for at least 100ms (or 2 seconds if midspan mode is enabled), and will repeat the detection cycle to ensure that the data in the port status register is up-to-date. if the port is in semi-auto mode and high power opera- tion is enabled, the port will not turn on in response to a power-on command unless the current detect result is detect good. any other detect result will generate a t start fault if a power-on command is received. if the port is not in high power mode, it will ignore the detection result and apply power when commanded, maintaining backwards compatibility with the ltc4259a. figure 12. pd detection figure 11. ieee 802.3af signature resistance ranges 4-point detection the ltc4274a/ltc4274c uses a 4-point detection method to discover pds. false-positive detections are minimized by checking for signature resistance with both forced-current and forced-voltage measurements. initially, two test cur- rents are forced onto the port (via the out pin) and the resulting voltages are measured. the detection circuitry subtracts the two v-i points to determine the resistive slope while removing offset caused by series diodes or leakage at the port (see figure 12). if the forced-current detection yields a valid signature resistance, two test voltages are then forced onto the port and the resulting currents are measured and subtracted. both methods must report valid resistances for the port to report a valid detection. pd signature resistances between 17k and 29k (typically) are detected as valid and reported as detect good in the resistance pd pse 0 10k 15k 4274ac f11 19k 26.5k 26.25k 23.75k 150 (nic) 20k 30k 33k first detection point second detection point valid pd 25k slope 275 165 current (a) 0v-2v offset voltage 4274ac f12
ltc4274a/ltc4274c 20 4274acfc applications information behavior in auto pin mode is similar to semi-auto; however, after detect good is reported and the port is classified (if classification is enabled), it is automatically powered on without further intervention. in standalone (auto pin) mode, the i cut and i lim thresholds are automatically set; see the reset and the auto/mid pin section for more information. the signature detection circuitry is disabled when the port is initially powered up with the auto pin low, in shutdown mode, or when the corresponding detect enable bit is cleared. detection of legacy pds proprietary pds that predate the original ieee 802.3af standard are commonly referred to today as legacy de- vices. one type of legacy pd uses a large common mode capacitance (>10f) as the detection signature. note that pds in this range of capacitance are defined as invalid, so a pse that detects legacy pds is technically noncompliant with the ieee spec. the ltc4274a/ltc4274c can be configured to detect this type of legacy pd. legacy detection is disabled by default, but can be manually enabled. when enabled, the port will report detect good when it sees either a valid ieee pd or a high-capacitance legacy pd. with legacy mode disabled, only valid ieee pds will be recognized. classification 802.3af classification a pd can optionally present a classification signature to the pse to indicate the maximum power it will draw while operating. the ieee specification defines this signature as a constant current draw when the pse port voltage is in the v class range (between 15.5v and 20.5v), with the current level indicating one of 5 possible pd classes. figure 13 shows a typical pd load line, starting with the slope of the 25k signature resistor below 10v, then transitioning to the classification signature current (in this case, class 3) in the v class range. table 5 shows the possible clas- sification values. table 5. classification values class result class 0 no class signature present; treat like class 3 class 1 3w class 2 7w class 3 13w class 4 25.5w (type 2) if classification is enabled, the port will classify the pd immediately after a successful detection cycle in semi-auto or auto pin modes, or when commanded to in manual mode. it measures the pd classification signature by ap- plying 18v for 12ms (both values typical) to the port via the out pin and measuring the resulting current; it then reports the discovered class in the port status register. if the ltc4274a/ltc4274c is in auto pin mode, it will additionally use the classification result to set the i cut and i lim thresholds. see the reset and the auto/mid pin section for more information. the classification circuitry is disabled when the port is initially powered up with the auto pin low, in shutdown mode, or when the corresponding class enable bit is cleared. figure 13. pd classification voltage (v class ) 0 current (ma) 60 50 40 30 20 10 0 5101520 4274ac f13 25 typical class 3 pd load line 48ma 33ma pse load line 23ma 14.5ma 6.5ma class 4 class 2 class 1 class 0 class 3 over current
ltc4274a/ltc4274c 21 4274acfc applications information 802.3at 2-event classification the 802.3at specification defines two methods of classify- ing a type 2 pd. the ltc4274a supports 802.3at 2-event classification. the ltc4274c does not support 2-event classification. one method adds extra fields to the ethernet lldp data protocol; although the ltc4274a/ltc4274c is compatible with this classification method, it cannot perform clas- sification directly since it doesnt have access to the data path. lldp classification requires the pse to power the pd as a standard 802.3af (type 1) device. it then waits for the host to perform lldp communication with the pd and update the pse port data. the ltc4274a/ltc4274c supports changing the i lim and i cut levels on the fly, al- lowing the host to complete lldp classification. the second 802.3at classification method, known as 2-event classification or ping-pong, is supported by the ltc4274a. a type 2 pd that is requesting more than 13w will indicate class 4 during normal 802.3af classification. if the ltc4274a sees class 4, it forces the port to a speci- fied lower voltage (called the mark voltage, typically 9v), pauses briefly, and then re-runs classification to verify the class 4 reading (figure 1). it also sets a bit in the high power status register to indicate that it ran the second classification cycle. the second cycle alerts the pd that it is connected to a type 2 pse which can supply type 2 power levels. 2-event ping-pong classification is enabled by setting a bit in the ports high power mode register. note that a ping- pong enabled port only runs the second classification cycle when it detects a class 4 device; if the first cycle returns class 0 to 3, the port assumes it is connected to a type 1 pd and does not run the second classification cycle. invalid type 2 class combinations the 802.3at specification defines a type 2 pd class sig- nature as two consecutive class 4 results; a class 4 fol- lowed by a class 0-3 is not a valid signature. in auto pin mode, the ltc4274a will power a detected pd regardless of the classification results, with one exception: if the pd presents an invalid type 2 signature (class 4 followed by class 0 to 3), the ltc4274a will not provide power and will restart the detection process. to aid in diagnosis, the port status register will always report the results of the last class pulse, so, for example, an invalid class 4Cclass 2 combination would report a second class pulse was run in the high power status register (which implies that the first cycle found class 4), and class 2 in the port status register. power control external mosfet, sense resistor summary the primary function of the ltc4274a/ltc4274c is to control the delivery of power to the pse port. it does this by controlling the gate drive voltage of an external power mosfet while monitoring the current via an external sense resistor and the output voltage at the out pin. this circuitry serves to couple the raw v ee input supply to the port in a controlled manner that satisfies the pds power needs while minimizing power dissipation in the mosfet and disturbances on the v ee backplane. the ltc4274a/ltc4274c is designed to use 0.25 sense resistors to minimize power dissipation. it also supports 0.5 sense resistors, which are the default when ltc4258/ ltc4259a compatibility is desired. inrush control once the command has been given to turn on a port, the ltc4274a/ltc4274c ramps up the gate pin of the ports external mosfet in a controlled manner. under normal power-up circumstances, the mosfet gate will rise until the port current reaches the inrush current limit level (typically 450ma), at which point the gate pin will be servoed to maintain the specified i inrush current. during this inrush period, a timer (t start ) runs. when output charging is complete, the port current will fall and the gate pin will be allowed to continue rising to fully enhance the mosfet and minimize its on-resistance. the final v gs is nominally 12v. the inrush period is maintained until the t start timer expires. at this time if the inrush current limit level is still exceeded the port will be turned back off and a t start fault reported.
ltc4274a/ltc4274c 22 4274acfc applications information current limit the ltc4274a/ltc4274c port includes two current limit- ing thresholds (i cut and i lim ), each with a corresponding timer (t cut and t lim ). setting the i cut and i lim thresholds depends on several factors: the class of the pd, the volt- age of the main supply (v ee ), the type of pse (type 1 or type 2), the sense resistor (0.5 or 0.25), the soa of the mosfet, and whether or not the system is required to implement class enforcement. per the ieee specification, the ltc4274a/ltc4274c will allow the port current to exceed i cut for a limited period of time before removing power from the port, whereas it will actively control the mosfet gate drive to keep the port current below i lim . the port does not take any action to limit the current when only the i cut threshold is exceeded, but does start the t cut timer. if the current drops below the i cut current threshold before its timer expires, the t cut timer counts back down, but at 1/16 the rate that it counts up. if the t cut timer reaches 60ms (typical) the port is turned off and the port t cut fault is set. this allows the current limit circuitry to tolerate intermittent overload signals with duty cycles below about 6%; longer duty cycle overloads will turn the port off. the i lim current limiting circuit is always enabled and actively limiting port current. the t lim timer is enabled only when the programmable t lim field is non-zero. this allows t lim to be set to a shorter value than t cut to provide more aggressive mosfet protection and turn off a port before mosfet damage can occur. the t lim timer starts when the i lim threshold is exceeded. when the t lim timer reaches 1.7ms (typ) times the programmable t lim field the port is turned off and the port t lim fault is set. when the t lim field is zero, t lim behaviors are tracked by the t cut timer, which counts up during both i lim and i cut events. i cut is typically set to a lower value than i lim to allow the port to tolerate minor faults without current limiting. per the ieee specification, the ltc4274a/ltc4274c will automatically set i lim to 425ma (shown in bold in table 6) during inrush at port turn-on, and then switch to the programmed i lim setting once inrush has completed. to maintain ieee compliance, i lim should be kept at 425ma for all type 1 pds, and 850ma if a type 2 pd is detected. i lim is automatically reset to 425ma when a port turns off. table 6. example current limit settings i lim (ma) internal register setting (hex) r sense = 0.5 r sense = 0.25 53 88 106 08 88 159 89 213 80 08 266 8a 319 09 89 372 8b 425 00 80 478 8e 531 92 8a 584 cb 638 10 90 744 d2 9a 850 40 c0 956 4a ca 1063 50 d0 1169 5a da 1275 60 e0 1488 52 49 1700 40 1913 4a 2125 50 2338 5a 2550 60 2975 52 i lim foldback the ltc4274a/ltc4274c features a two-stage foldback circuit that reduces the port current if the port voltage falls below the normal operating voltage. this keeps mosfet power dissipation at safe levels for typical 802.3af mos- fets, even at extended 802.3at power levels. current limit and foldback behavior are programmable. table 6 gives examples of recommended i lim register settings.
ltc4274a/ltc4274c 23 4274acfc applications information the ltc4274a/ltc4274c will support current levels well beyond the maximum values in the 802.3at specification. the shaded areas in table 6 indicate settings that may require a larger external mosfet, additional heat sinking, or enabling t lim . mosfet fault detection the ltc4274a/ltc4274c pse port is designed to toler- ate significant levels of abuse, but in extreme cases it is possible for the external mosfet to be damaged. a failed mosfet may short source to drain, which will make the port appear to be on when it should be off; this condition may also cause the sense resistor to fuse open, turning off the port but causing the ltc4274a/ltc4274c sense pin to rise to an abnormally high voltage. a failed mosfet may also short from gate to drain, causing the ltc4274a/ ltc4274c gate pin to rise to an abnormally high voltage. the ltc4274a/ltc4274c out, sense and gate pins are designed to tolerate up to 80v faults without damage. if the ltc4274a/ltc4274c sees any of these conditions for more than 180s, it disables all port functionality, reduces the gate drive pull-down current for the port and reports a fet bad fault. this is typically a permanent fault, but the host can attempt to recover by resetting the port, or by resetting the entire chip if a port reset fails to clear the fault. if the mosfet is in fact bad, the fault will quickly return, and the port will disable itself again. an open or missing mosfet will not trigger a fet bad fault, but will cause a t start fault if the ltc4274a/ltc4274c attempts to turn on the port. voltage and current readback the ltc4274a/ltc4274c measures the output voltage and current at the port with an internal a/d converter. port data is only valid when the port power is on. the converter has two modes: ? slow mode: 14 samples per second, 14.5 bits resolution ? fast mode: 440 samples per second, 9.5 bits resolution in fast mode, the least significant 5 bits of the lower byte are zeroes so that bit scaling is the same in both modes. disconnect the ltc4274a/ltc4274c monitors the port to make sure that the pd continues to draw the minimum specified current. a disconnect timer counts up whenever port current is below 7.5ma (typ), indicating that the pd has been disconnected. if the t dis timer expires, the port will be turned off and the disconnect bit in the fault event reg- ister will be set. if the current returns before the t dis timer runs out, the timer resets and will start counting from the beginning if the undercurrent condition returns. as long as the pd exceeds the minimum current level more often than t dis , it will stay powered. although not recommended, the dc disconnect feature can be disabled by clearing the dc disconnect enable bit. note that this defeats the protection mechanisms built into the ieee spec, since a powered port will stay powered after the pd is removed. if the still-powered port is subsequently connected to a non-poe data device, the device may be damaged. the ltc4274a/ltc4274c does not include ac discon- nect circuitry, but includes an ac disconnect enable bit to maintain compatibility with the ltc4259a. if the ac disconnect enable bit is set, dc disconnect will be used. shutdown pin the ltc4274a/ltc4274c includes a hardware shdn pin. when the shdn pin is pulled to dgnd, the port will be shut off immediately. the port remains shut down until re-enabled via i 2 c or a device reset in auto pin mode. masked shutdown the ltc4274a/ltc4274c provides a low latency port shedding feature to quickly reduce the system load when required. by allowing a pre-determined set of ports to be turned off, the current on an overloaded main power supply can be reduced rapidly while keeping high priority devices powered. each port can be configured to high or low priority; all low-priority ports will shut down within 6.5s after the msd pin is pulled low. if a port is turned off via msd, the corresponding detection and classification enable bits are cleared, so the port will remain off until the host explicitly re-enables detection.
ltc4274a/ltc4274c 24 4274acfc serial digital interface overview the ltc4274a/ltc4274c communicates with the host us- ing a standard smbus/i 2 c 2-wire interface. the ltc4274a/ ltc4274c is a slave-only device, and communicates with the host master using the standard smbus protocols. interrupts are signaled to the host via the int pin. the timing diagrams (figures 5 through 9) show typical com- munication waveforms and their timing relationships. more information about the smbus data protocols can be found at www.smbus.org. the ltc4274a/ltc4274c requires both the v dd and v ee supply rails to be present for the serial interface to function. bus addressing the ltc4274a/ltc4274cs primary serial bus address is 010xxxxb, with the lower four bits set by the ad3-ad0 pins; this allows up to 16 ltc4274a/ltc4274cs on a single bus. all ltc4274a/ltc4274cs also respond to the address 0110000b, allowing the host to write the same command (typically configuration commands) to multiple ltc4274a/ltc4274cs in a single transaction. if the ltc4274a/ltc4274c is asserting the int pin, it will also respond to the alert response address (0001100b) per the smbus spec. interrupts and smbalert most ltc4274a/ltc4274c port events can be configured to trigger an interrupt, asserting the int pin and alerting the host to the event. this removes the need for the host to poll the ltc4274a/ltc4274c, minimizing serial bus traffic and conserving host cpu cycles. multiple ltc4274a/ ltc4274cs can share a common int line, with the host using the smbalert protocol (ara) to determine which ltc4274a/ltc4274c caused an interrupt. register description for information on serial bus usage and device configura- tion and status, refer to the ltc4274a/ltc4274c software programming documentation. external component selection power supplies and bypassing the ltc4274a/ltc4274c requires two supply voltages to operate. v dd requires 3.3v (nominally) relative to dgnd. v ee requires a negative voltage of between C45v and C57v for type 1 pses, C51v to C57v for type 2 pses or C54.75v to C57v for ltpoe ++ pses, relative to agnd. the relation- ship between the two grounds is not fixed; agnd can be referenced to any level from v dd to dgnd, although it should typically be tied to either v dd or dgnd. v dd provides power for most of the internal ltc4274a/ ltc4274c circuitry, and draws a maximum of 3ma. a ceramic decoupling cap of at least 0.1f should be placed from v dd to dgnd, as close as practical to each ltc4274a/ ltc4274c chip. figure 14 shows a three component low dropout regula- tor for a negative supply to dgnd generated from the negative v ee supply. v dd is tied to agnd and dgnd is negative referenced to agnd. this regulator drives a single ltc4274a/ltc4274c device. in figure 15, dgnd is tied to agnd in this boost converter circuit for a positive v dd supply of 3.3v above agnd. this circuit can drive multiple ltc4274a/ltc4274c devices and opto couplers. applications information figure 14. negative ldo to dgnd 4274ac f14 r5 750k d1 cmhz4687-4.3v c1 0.1 f q2 cmp ta92 v ee v dd ltc4274a/ ltc4274c agnd v ee agnd dgnd
ltc4274a/ltc4274c 25 4274acfc applications information v ee is the main supply that provides power to the pd. because it supplies a relatively large amount of power and is subject to significant current transients, it requires more design care than a simple logic supply. for minimum ir loss and best system efficiency, set v ee near maximum amplitude (57v), leaving enough margin to account for transient over- or undershoot, temperature drift, and the line regulation specs of the particular power supply used. bypass capacitance between agnd and v ee is very impor- tant for reliable operation. if a short-circuit occurs at the output port it can take as long as 1s for the ltc4274a/ ltc4274c to begin regulating the current. during this time the current is limited only by the small impedances in the circuit and a high current spike typically occurs, causing a voltage transient on the v ee supply and possibly causing the ltc4274a/ltc4274c to reset due to a uvlo fault. a 1f, 100v x7r capacitor placed near the v ee pin is recommended to minimize spurious resets. isolating the serial bus the ltc4274a/ltc4274c includes a split sda pin (sdain and sdaout) to ease opto-isolation of the bidirectional sda line. ieee 802.3 ethernet specifications require that network segments (including poe circuitry) be electrically isolated from the chassis ground of each network interface device. however, network segments are not required to be isolated from each other, provided that the segments are connected to devices residing within a single building on a single power distribution system. for simple devices such as small poe switches, the isola- tion requirement can be met by using an isolated main power supply for the entire device. this strategy can be used if the device has no electrically conducting ports other than twisted-pair ethernet. in this case, the sdain and sdaout pins can be tied together and will act as a standard i 2 c/smbus sda pin. if the device is part of a larger system, contains additional external non-ethernet ports, or must be referenced to protective ground for some other reason, the power over ethernet subsystem (including all ltc4274a/ltc4274cs) must be electrically isolated from the rest of the system. figure 16 shows a typical isolated serial interface. the sdaout pin of the ltc4274a/ltc4274c is designed to drive the inputs of an opto-coupler directly. standard i 2 c/ smbus devices typically cannot drive opto-couplers, so u1 is used to buffer the signals from the host controller side. figure 15. positive v dd boost converter 4274ac f15 r54 56k c79 2200pf gnd ith/run ltc3803 v cc 2 5 v fb 1 3 ngate q15 fdc2512 q13 fmmt723 q14 fmmt723 sense 6 4 v ee c74 100f 6.3v c75 10f 16v l3 100h sumida cdrh5d28-101nc r51 4.7k 1% r53 4.7k 1% r52 3.32k 1% 3.3v at 400ma r55 806 1% r59 0.100 1%, 1w r56 47.5k 1% r57 1k d28 b1100 r58 10 r60 10 c73 10f 6.3v l4 10h sumida cdrh4d28-100nc + c77 0.22f 100v c78 0.22f 100v c76 10f 63v
ltc4274a/ltc4274c 26 4274acfc applications information figure 16. opto-isolating the i 2 c bus 4274ac f16 v dd int scl sdain sdaout ad0 ad1 ad2 ad3 dgnd agnd ltc4274a/ ltc4274c 0.1f 10f 2k 2k 0.1f 0.1f 2001 2001 2001 2001 u2 u3 u1 hcpl-063l hcpl-063l v dd cpu scl sda smbalert gnd cpu u1: fairchild nc7wz17 u2, u3: agilent hcpl-063l to controller isolated 3.3v isolated gnd +
ltc4274a/ltc4274c 27 4274acfc external mosfet careful selection of the power mosfet is critical to system reliability. ltc recommends either fairchild irfm120a, fdt3612, fdmc3612 or philips pht6nq10t for their proven reliability in type 1 and type 2 pse applications. non-standard applications that provide more current than the 850ma ieee maximum may require heat sinking and other mosfet design considerations. contact ltc ap- plications before using a mosfet other than one of these recommended parts. sense resistor the ltc4274a/ltc4274c is designed to use either 0.5 or 0.25 current sense resistors. for new designs 0.25 is recommended to reduce power dissipation; the 0.5 op- tion is intended for existing systems where the ltc4274a/ ltc4274c is used as a drop-in replacement for the ltc4258 or ltc4259a. the lower sense resistor values reduce heat dissipation. four commonly available 1 resistors (0402 or larger package size) can be used in parallel in place of a single 0.25 resistor. in order to meet the i cut and i lim accuracy required by the ieee specification, the sense resistors should have 1% tolerance or better, and no more than 200ppm/c temperature coefficient. port output cap the port requires a 0.22f cap across its output to keep the ltc4274a/ltc4274c stable while in current limit during startup or overload. common ceramic capacitors often have significant voltage coefficients; this means the capacitance is reduced as the applied voltage increases. to minimize this problem, x7r ceramic capacitors rated for at least 100v are recommended. esd/cable discharge protection ethernet ports can be subject to significant esd events when long data cables, each potentially charged to thousands of volts, are plugged into the low impedance of the rj45 jack. to protect against damage, the port requires a pair of clamp diodes; one to agnd and one to v ee (figure 10). an additional surge suppressor is required for each ltc4274a/ltc4274c chip from v ee to agnd. the diodes at the port steer harmful surges into the supply rails, where they are absorbed by the surge suppressor and the v ee bypass capacitance. the surge suppressor has the additional benefit of protecting the ltc4274a/ltc4274c from transients on the v ee supply. s1b diodes work well as port clamp diodes, and an smaj58a or equivalent is recommended for the v ee surge suppressor. layout guidelines strict adherence to board layout, parts placement and routing guidelines is critical for optimal current read- ing accuracy, ieee compliance, system robustness, and thermal dissipation. power delivery above 25.5w imposes additional com- ponent and layout restraints. specifically mosfet, sense resistor and transformer selection is crucial to safe and reliable system operation. contact ltc applications to obtain a full set of layout guidelines, example layouts and boms. applications information
ltc4274a/ltc4274c 28 4274acfc please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. package description uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701 rev c) 5.00 p 0.10 note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 37 1 2 38 bottom viewexposed pad 5.50 ref 5.15 0.10 7.00 p 0.10 0.75 p 0.05 r = 0.125 typ r = 0.10 typ 0.25 p 0.05 (uh) qfn ref c 1107 0.50 bsc 0.200 ref 0.00 C 0.05 recommended solder pad layout apply solder mask to areas that are not soldered 3.00 ref 3.15 0.10 0.40 p0.10 0.70 p 0.05 0.50 bsc 5.5 ref 3.00 ref 3.15 0.05 4.10 p 0.05 5.50 p 0.05 5.15 0.05 6.10 p 0.05 7.50 p 0.05 0.25 p 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 s 45o chamfer
ltc4274a/ltc4274c 29 4274acfc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 9/11 changed gate typ voltage to 12v. 3, 15, 21 revised v ild text under digital interface. 4 table 4 reference and caption changed to table 5. 20 revised power supply voltage figures under power supplies and bypassing. 24 text cut/lim changed to i cut /i lim in the related parts section. 30 specified smaj58a for zener diode. 30 b 1/12 changed ltpoe ++ power levels from 35w, 45w to 38.7w, 52.7w respectively. revised max value for v ild i 2 c input low voltage. clarified auto pin mode relationship to reset pin. 1, 2, 16, 17 4 18 c 8/12 table 1: changed twisted pair requirement from 2-pair to 4-pair for 38.7w and 52.7w 17
ltc4274a/ltc4274c 30 4274acfc ? linear technology corporation 2011 lt 0812 rev c ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com related parts part number description comments ltc4270/ltc4271 12-port poe/poe + /ltpoe ++ pse controller transformer isolation, supports type 1, type 2 and ltpoe ++ pds LTC4266 quad ieee 802.3at poe pse controller 2-event classification, programmable i cut /i lim LTC4266a/LTC4266c quad ieee 802.3at poe pse controller 13w through 90w support ltc4274 single ieee 802.3at poe pse controller 2-event classification, programmable i cut /i lim ltc4265 ieee 802.3at pd interface controller 100v, 1a internal switch, 2-event classification recognition ltc4267 ieee 802.3af pd interface with integrated switching regulator internal 100v, 400ma switch, dual inrush current, programmable class ltc4269-1 ieee 802.3at pd interface with integrated flyback switching regulator 2-event classification, programmable classification, synchronous no-opto flyback controller, 50khz to 250khz, auxiliary support ltc4269-2 ieee 802.3at pd interface with integrated forward switching regulator 2-event classification, programmable classification, synchronous forward controller, 100khz to 500khz, auxiliary support ltc4278 ieee 802.3at pd interface with integrated flyback switching regulator 2-event classification, programmable classification, synchronous no-opto flyback controller, 50khz to 250khz, 12v auxiliary support one complete isolated powered ethernet port typical application 4274ac ta02 1 2 3 4 5 6 7 8 2k 2k 1f 100v x7r 0.1 f 0.1 f 200 200 200 200 u2 u3 u1 hcpl-063l hcpl-063l v dd cpu scl sda gnd cpu smbalert to controller phy (network physical layer chip) 0.22f 100v x7r v ee sense gate out v dd scl sdain sdaout int r sense 0.25 q1 t1 l tc4274a/ ltc4274c dgnd agnd isolated C54v smaj58a s1b isolated 3.3v isolated gnd 0.01f 200v 0.01f 200v 0.01f 200v 0.01f 200v 75 75 75 75 rj45 connector 1000pf 2000v s s s s ss ss s s s s fb1 fb2 s1b

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